1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of operating the nonvolatile semiconductor memory device.
2. Description of Related Art
Nonvolatile semiconductor memory devices, such as flash memories, have been known which perform nonvolatile storage of data. In general, the flash memories perform an erase operation collectively in units of a sector or memory cell array. That is to say, erasing is performed at the erase operation by supplying negative voltage to gates of all memory cells after writing (programming) is performed to those memory cells in a sector to be erased. At this time, there are variations in threshold voltages at the memory cells after the erasing, due to variations in the properties of the memory cells in the sector. For this reason, it is possible that there is a memory cell where over-erasing is caused among the memory cells in the sector. To cope with such possibility, a verify operation is performed after the erase operation. With this erase-verify operation, judgment is made whether an over-erased memory cell is present or not and rewriting (reprogramming) is performed to such an over-erased memory cell.
As the related art, a flash memory device is disclosed in Japanese Laid-Open Patent Application JP-P2001-43693A (corresponding to U.S. Pat. No. 6,233,198B1). This memory device is a nonvolatile semiconductor memory device having a hierarchical word line structure. The memory device includes a plurality of sectors, a plurality of global word lines, a global word line selection circuit, a first local decoder, and a second local decoder. The plurality of sectors has memory cells, each of which is connected to the local word line. Each of the plurality of global word lines is arranged through the corresponding sector. The global word line selection circuit has a first global decoder for selecting one word line from odd-numbered global word lines and a second global decoder for selecting one word line from even-numbered global word lines. The first local decoder, which corresponds to each of the odd-numbered global word lines, drives one word line among corresponding local word lines to a word line voltage when a corresponding odd-numbered global word line is selected. The second local decoder, which corresponds to each of the even-numbered global word lines, drives one word line among corresponding local word lines to the word line voltage when a corresponding even-numbered global word line is selected. Each of the first and second local decoders has a plurality of drivers each connected to corresponding local word lines. Each of the drivers is composed of a pull-up transistor for connecting a local word line that corresponds to a signal of a corresponding global word line to a row partial decoder, and a pull-down transistor for connecting the corresponding local word line to a block decoder in accordance with the signal of the corresponding global word line.
Japanese Laid-Open Patent Application JP-A-Heisei 10-214495 (corresponding to U.S. Pat. No. 5,973,963A) discloses a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes an internal power supply generation circuit, a power switching circuit, a memory cell array, and a row decoder circuit section. The internal power supply generation circuit receives a given external voltage and outputs negative voltage and high voltage larger than the given external voltage. The power switching circuit switches one of the high voltage and the negative voltage to another, and outputs it. The memory cell array has a plurality of memory cell transistors capable of electrical erasing and writing arranged in row and column directions in a matrix form. The row decoder circuit section selects one of the word lines of the memory cell array in accordance with an input address, outputs an output that corresponds to the negative voltage or high voltage to the selected word line in accordance with selection modes of erasing or writing, and outputs ground potential to unselected word lines. The row decoder circuit section has a main decoder, a predecoder, and a word line driver. The main decoder in accordance with the input address, outputs ground potential and the external voltage potential from selected first and second output nodes, and outputs the external voltage potential and ground potential when negative voltage is supplied to the selected word line and high voltage potential and ground potential when high voltage is supplied to the selected word line from unselected first and second output nodes. The predecoder outputs negative voltage potential or the external voltage potential from a selected output node and ground potential from an unselected output node in accordance with the input address and selection modes. The word line driver connects the first and second output nodes of the main decoder with the output nodes of the predecoder, and outputs negative voltage potential or the external voltage potential that are in accordance with the selection modes to a selected word line and ground potential to unselected word lines.
Japanese Laid-Open Patent Application JP-P2005-317138A (corresponding to US2005/0243602A1) discloses a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a memory cell, a memory cell array, a bit line, a word line, a latch circuit, a voltage generation circuit, a first row decoder, a second row decoder, a first separatory transistor, and a second separatory transistor. The memory cell includes a memory cell transistor having a floating gate and a control gate. The memory cell array has the memory cells arranged in a matrix form. The bit line is electrically and commonly connected between drains of the memory cell transistors in the same column. The word line is commonly connected between control gates of the memory cell transistors in the same row. The latch circuit is provided in correspondence to the bit line and stores written data. The voltage generation circuit generates negative voltage and positive voltage. The first row decoder is provided for each word line and applies positive voltage generated by the voltage generation circuit to the word line at the time of writing and erasing. The second row decoder is provided for each word line and applies negative voltage generated by the voltage generation circuit to the word line at the time of writing and erasing. The first separatory transistor is provided for each word line and performs switching between the first row decoder and the word line. The second separatory transistor is provided for each word line and performs switching between the second row decoder and the word line.
We have now discovered the following facts.
Variations in threshold voltages at memory cells at the time of erasing as mentioned above have not caused problems so far since the variations are within a given allowable range. However, it is expected with the miniaturization of memory cells that the variations in threshold voltages rise to a level that no longer can be ignored. In that case, for example, there is a possibility that over-erasing is too spread to be coped with by the typical erase-verify operation. For this reason, a technique is desired that can control variations in threshold voltages at memory cells at the time of erasing to stably perform an erase operation, responding to the miniaturization of memory cells.
The study by the inventors of the present invention has revealed that it is preferable to perform an erase operation in units of not a sector but a word line in a sector, as a method of controlling variations in threshold voltages at memory cells at the time of erasing. This makes it possible to narrow distribution of threshold voltages as a result of reduction in the number (population parameter) of memory cells to be erased at one erase operation. In other words, a range of variations in threshold voltages can be kept narrow.
In addition, the following phenomenon may be caused when erasing is performed to a sector collectively. When an over-erased memory cell is present on a bit line, read current is more likely to flow through the over-erased memory cell compared with other memory cells on the bit line. Therefore, when an over-erased memory cell is caused in performing collective erasing to a sector, it is difficult at the time of erase-verify to correctly read data of the other memory cells that share the bit line with the over-erased memory cell. As a result, it is difficult to correctly perform erase-verify.
However, when an erase operation is performed in units of a word line as mentioned above, erasing and erase-verify are performed to each word line after collective writing, or erasing and erase-verify are performed to each word line after writing is performed to each word line. In other words, erasing, erase-verify, and rewriting at least are performed in units of a word line. Consequently, an over-erased memory cell is no longer present on the same bit line. Then, it is possible to prevent the above phenomenon caused in performing collective erasing to a sector.
As explained above, it is effective to perform an erase operation in units of a word line in order to control variations in threshold voltages at memory cells at the time of erasing. However, when a row local decoder with four transistors shown in FIG. 2 of Japanese Laid-Open Patent Application JP-P2001-43693A is used, selecting one word line (selected word line) causes other word lines that are not selected (unselected word line) to be in an open state (floating state), or high impedance state. As a result, the unselected word lines are susceptible to the effect of voltage noise, which may cause false operation.
In addition, Japanese Laid Open Patent Application JP-A-Heisei 10-214495 discloses a structure where desired positive voltage and GND are applied to a selected word line and unselected word lines respectively, by a word line driver circuit 19. In this case, problems have not been posed so far since an erase operation is not performed collectively to a sector. However, when erasing is performed in units of a word line, there is a possibility that erasing is also caused to a memory cell on an unselected word line, which has been revealed by the inventors' study. That is to say, the inventors' study has revealed that erasing can be caused to a memory cell on an unselected word line as well as that on a selected word line by electrons being drawn out by positive voltage, when negative voltage and GND are applied to a selected word line and unselected word lines respectively and the positive voltage is applied as a substrate voltage at the time of erasing. Occurrence of erasing to a memory cell on an unselected word line, which causes over-erasing and so on, is not preferable. It is desired to provide a technique to control variations in threshold voltages at memory cells at the time of erasing more appropriately and precisely without adversely affecting memory cells on word lines other than a selected word line.
Additionally, it is necessary to apply a voltage that is high to a certain degree between a gate of a memory cell and a substrate in order to satisfy erasing speed, when erasing is performed not collectively to a sector but in units of a word line to ultimately complete erasing of a whole sector. In this case, it is not possible to apply a high voltage to only one of the gate and the substrate (e.g. gate voltage is 10 V while substrate voltage is 0 V), considering withstand voltage and so forth of a device itself. Therefore, it is necessary to apply negative voltage as a gate voltage and positive voltage as a substrate voltage (e.g. the gate voltage is −5 V while the substrate voltage is +5 V). In this case, this related art does not make it possible to control variations in erasing distribution, where +5 V voltage is applied to erasing unselected cells.